ics525-01/02/11/12 mds 525-01/02/11/12 q 1 revision 101105 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com user configurable clock description the ics525-01/02/11/12 are the most flexible way to generate a high-quality, high-accuracy, high-frequency clock output from an inexpensive crystal or clock input. the user can configure the device to produce nearly any output frequency from any input frequency by grounding or floating the select pins. neither microcontroller, software, nor device programmer are needed to set the frequency. using phase-locked loop (pll) techniques, the device accepts a standard fundamental mode, inexpensive crystal to produce output clocks up to 250 mhz. it can also produce a highly accurate output clock from a given input clock, keeping them frequency locked together. for similar capability with a serial interface, use the ics307. for simple multipliers to produce common frequencies, refer to the ics50x family of parts, which are smaller and more cost effective. these products are intended for clock generation. they have low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. for applications which require defined input to output timing, use the ics527-01. features ? packaged as 28-pin ssop (150 mil body) ? industrial and commercial versions available in pb (lead) free package ? user determines the output frequency by setting all internal dividers ? eliminates need for custom oscillators ? no software needed ? online calculator determines register settings ? pull-ups on all select inputs ? input crystal frequency of 5 - 27 mhz ? input clock frequency of 2 - 50 mhz ? very low jitter ? duty cycle of 45/55 up to 200 mhz ? operating voltage of 3.0 v or 5.5 v ? ideal for oscillator replacement ? industrial temperature version available ? for zero delay, refer to the ics527 block diagram vdd gnd 2 2 clk ref reference divider phase comparator, charge pump, and loop filter vco vco divider output divider 9 73 r6:r0 v8:v0 s2:s0 x1/iclk x2 crystal or clock input optional crystal capacitors crystal oscillator pd
user configurable clock mds 525-01/02/11/12 q 2 revision 101105 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-01/02/11/12 pin assignment pin descriptions key: i(pu) = input with internal pull-up resistor; x1, x2 = crystal connections 18 7 17 8 16 9 15 x1/iclk 10 x2 11 gnd 12 clk 13 v0 14 v1 gnd pd v8 v2 v7 v5 v3 v6 22 21 20 19 v4 ref 5 6 s2 vdd vdd 24 23 r0 3 4 s0 s1 r1 26 25 r2 1 2 r5 r6 r3 28 27 r4 ics525-01/-02/-11/-12 pin number pin name pin type pin description 1, 2, 24-28 r5, r6, r0-r4 i(pu) reference divider word input pins determi ned by user. forms a binary number from 0 to 127. 3, 4, 5 s0, s1, s2 i(pu) select pins for output divider determined by user. see table on page 3 6, 23 vdd power connect to vdd. 7 x1/iclk x1 crystal connection. connect to a parallel resonant fundamental crystal or input clock. 8 x2 x2 crystal connection. connect to a crystal or leave unconnected for clock. 9, 20 gnd power connect to ground. 10 - 18 v0 - v8 i(pu) vco divider word input pins determined by user. forms a binary number from 0 to 511. 19 pd input power-down. active low. turns off en tire chip when low. clock outputs stop low. 21 clk output output clock determined by status of r0-r6, v-v8, s0-s2, and input frequency. 22 ref output reference output. buffered crystal oscillator (or clock ) output.
user configurable clock mds 525-01/02/11/12 q 3 revision 101105 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-01/02/11/12 ics525-01 output frequency and output divider table ics525-02 output frequency and output divider table ICS525-11 output frequency and output divider table s2 pin 5 s1 pin 4 s0 pin 3 clk output divider output frequency range (mhz) vdd = 5 v vdd = 3.3 v 0 - 70 c -40 to +85 c 0 - 70 c -40 to +85 c 0 0 0 10 3?26 3?23 3?18 3?16 0 0 1 2 15?160 15?140 15?100 15?90 0 1 0 8 3.75?40 3.75?36 3.75?25 3.75?22 0 1 1 4 7.5?80 7.5?72 7.5?50 7.5?45 1 0 0 5 6?50 6?45 6?34 6?30 1 0 1 7 4?40 4?36 4?26 4?23 1 1 0 9 3.3?33.3 3.3?30 3.3?20 3.3?18 1 1 1 6 5?53 5?47 5?27 5?24 s2 pin 5 s1 pin 4 s0 pin 3 clk output divider output frequency range (mhz) vdd = 5 v vdd = 3.3 v -40 to +85 c -40 to +85 c 0 0 0 6 5?67 5?40 0 0 1 2 15?200 15?120 0 1 0 8 3.75?50 3.75?30 0 1 1 4 7.5?100 7.5?60 1 0 0 5 6?80 6?48 1 0 1 7 4?57 4?34 1 1 0 1 30?250 30?200 1 1 1 3 10?133 10?80 s2 pin 5 s1 pin 4 s0 pin 3 clk output divider output frequency range (mhz) vdd = 5 v vdd = 3.3 v 0 - 70 c -40 to +85 c 0 - 70 c -40 to +85 c 0 0 0 10 0.75?6.5 0.75?5.75 0.75?4.5 0.75?4 0 0 1 2 3.75?40 3.75?35 3.75?25 3.75?22.5 0 1 0 8 0.94?10 0.94?9 0.94?6.25 0.94?5.5 0 1 1 4 1.875?20 1.875?18 1.875?12.5 1.875?11.25 1 0 0 5 1.5?12.5 1.5?11.25 1.5?8.5 1.5?7.5 1 0 1 7 1?10 1?9 1?6.5 1?5.75 1 1 0 9 0.83?8.33 0.83?7.5 0.83?5 0.83?4.5 1 1 1 6 1.25?13.25 1.25?11.75 1.25?6.75 1.25?6
user configurable clock mds 525-01/02/11/12 q 4 revision 101105 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-01/02/11/12 ics525-12 output frequency and output divider table s2 pin 5 s1 pin 4 s0 pin 3 clk output divider output frequency range (mhz) vdd = 5 v vdd = 3.3 v -40 to +85 c -40 to +85 c 0 0 0 6 1.25?16.75 1.25?10 0 0 1 2 3.75?50 3.75?30 0 1 0 8 0.94?12.5 0.94?7.5 0 1 1 4 1.875?25 1.875?15 1 0 0 5 1.5?20 1.5?12 1 0 1 7 1?14.25 1?8.5 1 1 0 1 7.5?62.5 7.5?50 1 1 1 3 2.5?33.25 2.5?20
user configurable clock mds 525-01/02/11/12 q 5 revision 101105 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-01/02/11/12 external components/crystal selection decoupling capacitors the ics525-01/02/11/12 requries two 0.01f decoupling capacitors to be connected between vdd and gnd, one on each side of the chip. the capacitor must be connected close to the device to minimize lead inductance. external resistors a 33 ? series termination resistor should be used on the clk and ref pins. crystal load capacitors the approximate total on-chip capacitance for a crystal is 16 pf, so a parallel resonant, fundamental mode crystal with this value of load (correlation) capacitance should be used. for crysta ls with a specified load capacitance greater than 16 pf, crystal capacitors may be connected from each of the pins x1 and x2 to ground as shown in the block diagram. the value (in pf) of these crystal caps should be (cl -16)*2, where cl is the crystal load capacitance in pf. these external capacitors are only required for applications where the exact frequency is critical. for a clock input, connect to x1 and leave x2 unconnected (no capacitors on either). determining the output frequency users have full control in setting the desired output frequency over the range shown in the tables on pages 3-4. to replace a standard oscillator, users should connect the divider select input pins directly to ground (or vdd, although this is not required because of internal pull-ups) during pr inted circuit board layout. the ics525 will automatically produce the correct frequency when all components are soldered. it is also possible to connect the inputs to parallel i/o ports to switch frequencies. by choosing divides carefully, the number of inputs which need to be changed can be minimized. observe the restrictions on allowed values of vdw and rdw. configuration pin settings the output of the ics525 can be determined by the following simple equation: where: reference divider word (rdw) = 0 to 127 (0 not permitted for ics525-01/-11) vco divider word (vdw) = 0 to 511 (0, 1, 2, 3 not permitted for ics525-01/-11) output divider (od) = values on pages 3-4 also, the following operating ranges should be observed: 1. the output frequency must be in the ranges listed on pages 3-4. 2. the phase detector frequency must be above 200 khz. since all of the inputs have pull-up resistors, it is only necessary to ground the pins that need to be set to zero. which part to use? the ics525-01 is the original configurable clock. the ics525-02 has a higher maximum output grequency and a slightly different set of output dividers. the ICS525-11 has the same divider set as the -01 but is optimized for low frequency operation. the ics525-12 has the same divider set as the -02 but is optimized for low frequency operation. to determine the best combination of vco, reference, and output divide, use the ics525 calculator on our web site. clk frequency input frequency 2x vdw 8 + () rdw 2 + () od ? -------------------------------------------- - = 200khz inputfrequency rdw 2 + () ----------------------------------------------- <
user configurable clock mds 525-01/02/11/12 q 6 revision 101105 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-01/02/11/12 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics525-01/02/11/12. these ratings, which are standard values for ics commercia lly rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. elec trical parameters are guaranteed on ly over the reco mmended operating temperature range. dc electrical characteristics unless stated otherwise, vdd = 3.3 v item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature, commercial 0 to +70 c ambient operating temperature, industrial -40 to +85 c storage temperature -65 c to 150 c junction temperature 125 c soldering temperature 260 c (max. of 10 seconds) parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 5.5 v operating supply current idd 60 mhz out, no load, 15 mhz crystal, ics525-01/02 only 8ma operating supply current idd 40 mhz out, 15 mhz crystal, ICS525-11/12 only 6ma operating supply current, power-down idd pin 19 = 0, note 1 4 a input high voltage v ih 2v input low voltage v il 0.8 v input high voltage, x1/iclk only v ih iclk (pin7) vdd/2+1 vdd/2 v input low voltage, x1/iclk only v il iclk (pin7) vdd/2 vdd/2-1 v output high voltage v oh i oh = -12 ma vdd-0.4 v output low voltage v ol i ol = 12 ma 0.4 v
user configurable clock mds 525-01/02/11/12 q 7 revision 101105 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-01/02/11/12 ac electrical characteristics unless stated otherwise, vdd = 3.3 v short circuit current clk and ref outputs 55 ma input capacitance c in v, r, s pins and pin 19 4 pf on-chip pull-up resistor r pu v, r, s pins and pin 19 270 k ? parameter symbol conditions min. typ. max. units input frequency f in crystal input 5 27 mhz clock input 2 50 mhz output clock rise time 0.8 to 2.0 v 1 ns output clock fall time 2.0 to 0.8 v 1 ns output clock duty cycle, od = 2, 4, 6, 8, or 10 at vdd/2 45 49 to 51 55 % output clock duty cycle, od = 3, 5, 7, or 9 at vdd/2 40 60 % output clock duty cycle, od = 1 (-02 and -12 only) at vdd/2 35 65 power-down time, pd low to clocks stopped 50 ns power-up time, pd high to clocks stable 10 ms absolute clock period jitter, ics525-01, note 2 t ja deviation from mean 140 ps one sigma clock period jitter, ics525-01, note 2 t js one sigma 45 ps absolute clock period jitter, ics525-02, note 2 t ja deviation from mean 85 ps one sigma clock period jitter, ics525-02, note 2 t js one sigma 30 ps absolute clock period jitter, ICS525-11, note 2 t ja deviation from mean 160 ps one sigma clock period jitter, ICS525-11, note 2 t js one sigma 40 ps absolute clock period jitter, ics525-12, note 2 t ja deviation from mean 160 ps one sigma clock period jitter, ics525-12, note 2 t js one sigma 40 ps parameter symbol conditions min. typ. max. units
user configurable clock mds 525-01/02/11/12 q 8 revision 101105 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-01/02/11/12 note 1: phase relationship between input and output can change at power-up. for a fixed phase relationship, see the ics527. note 2: for 16 mhz, 100 mhz output. use the -02 for lowest jitter. package outline and package dimensions (28-pin ssop, 150 mil body) package dimensions are kept current with jedec publication no. 95, mo-153 index area 1 2 28 d e1 e seating plane a 1 a a 2 e - c - b aaa c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a 1.351.75.053.069 a1 0.10 0.25 .0040 .010 a2 -- 1.50 -- .059 b 0.200.30.008.012 c 0.180.25.007.010 d 9.80 10.00 .386 .394 e 5.806.20.228.244 e1 3.80 4.00 .150 .157 e 0.635 basic 0.025 basic l 0.401.27.016.050 0 8 0 8 aaa -- 0.10 -- 0.004
user configurable clock mds 525-01/02/11/12 q 9 revision 101105 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-01/02/11/12 ordering information parts that are ordered with a "lf" suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments part / order number marking shipping packaging package temperature ics525-01r ics525-01r tubes 28-pin ssop 0 to +70 c ics525-01rt ics525-01r tape and reel 28-pin ssop 0 to +70 c ics525-01rlf ics525-01rlf tubes 28-pin ssop 0 to +70 c ics525-01rlft ics525-01rlf tape and reel 28-pin ssop 0 to +70 c ics525-01ri ics525-01ri tubes 28-pin ssop -40 to +85 c ics525-01rit ics525-01ri tape and reel 28-pin ssop -40 to +85 c ics525-01rilf ics525-01rilf tubes 28-pin ssop -40 to +85 c ics525-01rilft ics525-01rilf tape and reel 28-pin ssop -40 to +85 c ics525r-02i ics525r-02i tubes 28-pin ssop -40 to +85 c ics525r-02it ics525r-02i tape and reel 28-pin ssop -40 to +85 c ics525r-02ilf ics525r-02ilf tubes 28-pin ssop -40 to +85 c ics525r-02ilft ics525r-02ilf tape and reel 28-pin ssop -40 to +85 c ics525r-11 ics525r-11 tubes 28-pin ssop 0 to +70 c ics525r-11t ics525r-11 tape and reel 28-pin ssop 0 to +70 c ics525r-11lf ics525r-11lf tubes 28-pin ssop 0 to +70 c ics525r-11lft ics525r-11lf tape and reel 28-pin ssop 0 to +70 c ics525ri-11 ics525ri-11 tubes 28-pin ssop -40 to +85 c ics525ri-11t ics525ri-11 tape and reel 28-pin ssop -40 to +85 c ics525ri-11lf ics525ri-11lf tubes 28-pin ssop -40 to +85 c ics525ri-11lft ics525ri-11lf tape and reel 28-pin ssop -40 to +85 c ics525ri-12 ics525ri-12 tubes 28-pin ssop -40 to +85 c ics525ri-12t ics525ri-12 tape and reel 28-pin ssop -40 to +85 c ics525ri-12lf ics525ri-12lf tubes 28-pin ssop -40 to +85 c ics525ri12lft ics525ri-12lf tape and reel 28-pin ssop -40 to +85 c
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